CY74FCT377T数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The \\x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Function, Pinout, and Drive Compatible With FCT and F Logic
• Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Ioff Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

• Fully Compatible With TTL Input and Output Logic Levels
• Clock Enable for Address and Data Synchronization Application
• Eight Edge-Triggered D-Type Flip-Flops
• CY54FCT377T
• 32-mA Output Sink Current
• 12-mA Output Source Current

• CY74FCT377T
• 64-mA Output Sink Current
• 32-mA Output Source Current