CY74FCT823CTSOC.B中文资料德州仪器数据手册PDF规格书

Function, Pinout, and Drive Compatible

With FCT, F Logic, and AM29823

Reduced VOH (Typically = 3.3 V) Version of

Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

64-mA Output Sink Current

32-mA Output Source Current

High-Speed Parallel Register With

Positive-Edge-Triggered D-Type Flip-Flops

Buffered Common Clock-Enable (EN) and

Asynchronous-Clear (CLR) Inputs

3-State Outputs

description

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and

provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a

9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing

in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.

This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading

at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.