CY74FCT823ATSOC集成电路（IC）的触发器规格书PDF中文资料

CY74FCT823ATSOC属于集成电路（IC）的触发器。由美国德州仪器公司制造生产的CY74FCT823ATSOC触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

Function, Pinout, and Drive Compatible

With FCT, F Logic, and AM29823

Reduced VOH (Typically = 3.3 V) Version of

Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

64-mA Output Sink Current

32-mA Output Source Current

High-Speed Parallel Register With

Positive-Edge-Triggered D-Type Flip-Flops

Buffered Common Clock-Enable (EN) and

Asynchronous-Clear (CLR) Inputs

3-State Outputs

description

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and

provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a

9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing

in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.

This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading

at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.