CY54FCT841T数据手册TI中文资料规格书

描述 Description

The \\x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \\x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The \\x92FCT841T devices\\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
• Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Ioff Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

• Fully Compatible With TTL Input and Output Logic Levels
• High-Speed Parallel Latches
• Buffered Common Latch-Enable Input
• 3-State Outputs
• CY54FCT841T
• 32-mA Output Sink Current
• 12-mA Output Source Current

• CY74FCT841T
• 64-mA Output Sink Current
• 32-mA Output Source Current