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CSP2510C集成电路(IC)的时钟发生器PLL频率合成器规格书PDF中文资料

CSP2510C
厂商型号

CSP2510C

参数属性

CSP2510C 封装/外壳为24-TSSOP(0.173",4.40mm 宽);包装为管件;类别为集成电路(IC)的时钟发生器PLL频率合成器;产品描述:IC PLL CLK DRIVER 3.3V 24-TSSOP

功能描述

3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

封装外壳

24-TSSOP(0.173",4.40mm 宽)

文件大小

262.75 Kbytes

页面数量

10

生产厂商 Renesas Technology Corp
企业简称

RENESAS瑞萨

中文名称

瑞萨科技有限公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-5-17 8:00:00

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CSP2510C规格书详情

DESCRIPTION:

The CSP2510C is a high performance, low-skew, low-jitter, phase-lock

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CSP2510C

operates at 3.3V.

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Output signal duty cycles are adjusted to 50 percent, independent of the

duty cycle at CLK. The outputs can be enabled or disabled via the control

G input. When the G input is high, the outputs switch in phase and frequency

with CLK; when the G input is low, the outputs are disabled to the logic-low

state.

Unlike many products containing PLLs, the CSP2510C does not require

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSP2510C requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL

can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510C is specified for operation from 0°C to +85°C. This

device is also available (on special order) in Industrial temperature range

(-40°C to +85°C). See ordering information for details.

FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 133MHz: < ±150ps

• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz

• Spread Spectrum Compatible

• Operating frequency 25MHz to 140MHz

• Available in 24-Pin TSSOP package

产品属性

  • 产品编号:

    CSP2510CPG8

  • 制造商:

    Renesas Electronics America Inc

  • 类别:

    集成电路(IC) > 时钟发生器,PLL,频率合成器

  • 包装:

    管件

  • 类型:

    PLL 驱动器,零延迟缓冲器

  • PLL:

    带旁路

  • 输入:

    时钟

  • 输出:

    时钟

  • 比率 - 输入:

    1:10

  • 差分 - 输入:

    无/无

  • 频率 - 最大值:

    140MHz

  • 分频器/倍频器:

    无/无

  • 电压 - 供电:

    3V ~ 3.6V

  • 工作温度:

    0°C ~ 85°C

  • 安装类型:

    表面贴装型

  • 封装/外壳:

    24-TSSOP(0.173",4.40mm 宽)

  • 供应商器件封装:

    24-TSSOP

  • 描述:

    IC PLL CLK DRIVER 3.3V 24-TSSOP

供应商 型号 品牌 批号 封装 库存 备注 价格
IDT
01+
TSOP24
3400
全新原装进口自己库存优势
询价
IDT
18+
TSSOP24
24046
全新原装现货,可出样品,可开增值税发票
询价
IDT
24+
NA/
3384
原装现货,当天可交货,原型号开票
询价
IDT
24+
TSOP
80000
只做自己库存,全新原装进口正品假一赔百,可开13%增
询价
IDT
1948+
TSOP24
6852
只做原装正品现货!或订货假一赔十!
询价
AGERE
23+
SOP
3200
全新原装、诚信经营、公司现货销售!
询价
IDT
21+
24TSSOP
13880
公司只售原装,支持实单
询价
IDT
1405+
TSSOP24
1867
一级代理,专注军工、汽车、医疗、工业、新能源、电力
询价
IDT
24+
SSOP24L
4652
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
CSP2510CPG8
1276
1276
询价