3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

DESCRIPTION: The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

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RENESAS

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3.3V Phase-Lock Loop Clock Driver

Renesas

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Package：24-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLK DRIVER 3.3V 24-TSSOP

Renesas Electronics America Inc

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：托盘 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK DVR ZD BUFFER PLL 24TSSOP

Renesas Electronics America Inc

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLK DRIVER 3.3V 24-TSSOP

Renesas Electronics America Inc