丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011UB；Package：TSSOP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CM011UB；Package：TSSOP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CM012B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM012B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM015B；Package：TSSOP；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

文件：686.94 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CM015B；Package：TSSOP；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

文件：688.43 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CM015B；Package：TSSOP；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

文件：686.94 Kbytes 页数：16 Pages

TI

德州仪器