型号：74CBTLV3861DGVRG4.B；Package：TVSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861DGVR；Package：TVSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861DGVR；Package：TVSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

文件：695.31 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861DGVR.B；Package：TVSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PW；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PW；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

文件：695.31 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PW.B；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PWR；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PWR；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

文件：695.31 Kbytes 页数：19 Pages

TI2

德州仪器

型号：SN74CBTLV3861PWR.B；Package：TSSOP；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

文件：697.46 Kbytes 页数：19 Pages

TI2

德州仪器