丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

文件：1.18376 Mbytes 页数：26 Pages

TI

德州仪器