Dual P-Channel Enhancement Mode Field Effect Transistor

FEATURES ■ 40V, 18A, RDS(ON) = 5.1mΩ @VGS = 10V. RDS(ON) = 7.5mΩ @VGS = 4.5V. ■ Super high dense cell design for extremely low RDS(ON). ■ High power and current handing capability. ■ Lead free product is acquired. ■ Surface mount Package.

文件：405.62 Kbytes 页数：4 Pages

CET

华瑞

N-Channel 40-V (D-S) MOSFET

FEATURES • Halogen-free According to IEC 61249-2-21 • TrenchFET® Power MOSFET • 100 Rg and UIS Tested APPLICATIONS • Notebook CPU Core - High-Side Switch

文件：982.06 Kbytes 页数：9 Pages

VBSEMI

微碧半导体

N Channel MOSFET

CET

华瑞

QUAD CLOCKED D LATCH

Description The HCC4000B series is composed of close to 80 monolithic types built with Metal Oxide Complementary technology. It provides Designers with high voltage noise tolerant complete Logic series. It radiation hardness and immunity to Heavy Ions make this series to be usable in the

文件：301.45 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件：60.89 Kbytes 页数：6 Pages

PHI

PHI

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件：60.89 Kbytes 页数：6 Pages

PHI

PHI