3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER

1FEATURES · Qualified for Automotive Applications · Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications · Spread-Spectrum Clock Compatible · Operating Frequency: 24 MHz to 200 MHz · Low Jitter (Cycle-to-Cycle):

文件：469.89 Kbytes 页数：15 Pages

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德州仪器

CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver

1 Features 1• Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications • Spread Spectrum Clock Compatible • Operating Frequency: 24 MHz to 200 MHz • Low Jitter (Cycle-to-Cycle):

文件：862.54 Kbytes 页数：25 Pages

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德州仪器

3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER

文件：225.62 Kbytes 页数：10 Pages

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德州仪器

适用于兼容扩展频谱的同步、DRAM 和通用应用的汽车 PLL 时钟驱动器

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series- • Qualified for Automotive Applications\n• Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications\n• Spread-Spectrum Clock Compatible\n• Operating Frequency: 24 MHz to 200 MHz\n• Low Jitter (Cycle-to-Cycle): Range 66 MHz to 200 MHz\n• Distributes One Clock Input to One ;

TI

德州仪器