CDCVF111数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN)\\ to nine pairs of differential clock (Y, Y)\\ outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.
The VREF output can be strapped to the CLKIN\\ input for a single-ended CLKIN input.
The CDCVF111 is characterized for operation from –40°C to 85°C.

特性 Features

• Low-Output Skew for Clock-Distribution Applications
• Differential Low-Voltage Pseudo-ECL (LVPECL) Compatible Inputs and Outputs
• Distributes Differential Clock Inputs to Nine Differential Clock Outputs
• Output Reference Voltage (VREF) Allows Distribution From a Single-Ended Clock Input
• Packaged In a 28-Pin Plastic Chip Carrier