CDCP1803中文资料具有可编程分频器的 1:3 LVPECL 时钟缓冲器数据手册TI规格书

描述 Description

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines. The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

特性 Features

• Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
• Low-Output Skew 15 ps (Typical)
• Signaling Rate Up to 800-MHz LVPECL
• Provides VBB Bias Voltage Output for Single-Ended Input Signals
• 24-Terminal QFN Package (4 mm × 4 mm)
• Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS

简介

CDCP1803属于集成电路（IC）的时钟缓冲器驱动器。由TI制造生产的CDCP1803时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。