CDCLVP215中文资料双路 1:5 高速 LVPECL 扇出缓冲器数据手册TI规格书

描述 Description

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP215 is characterized for operation from –40°C to 85°C.

特性 Features

• 2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
• Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
• Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
• Available in the QFN32 Package
• Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
• APPLICATIONS
- Designed for Driving 50- Transmission Lines High Performance Clock Distribution