CDCLVP1208集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

CDCLVP1208属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的CDCLVP1208时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

1• 2:8 Differential Buffer

• Selectable Clock Inputs Through Control terminal

• Universal Inputs Accept LVPECL, LVDS, and

LVCMOS/LVTTL

• Eight LVPECL Outputs

• Maximum Clock Frequency: 2 GHz

• Maximum Core Current Consumption: 73 mA

• Very Low Additive Jitter: <100 fs,rms in 10 kHz to

20 MHz Offset Range:

– 57 fs, rms (typical) at 122.88 MHz

– 48 fs, rms (typical) at 156.25 MHz

– 30 fs, rms (typical) at 312.5 MHz

• 2.375-V to 3.6-V Device Power Supply

• Maximum Propagation Delay: 450 ps

• Maximum Output Skew: 20 ps

• LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

• Industrial Temperature Range: –40°C to 85°C

• Supports 105°C PCB Temperature

(Measured with a Thermal Pad)

• ESD Protection Exceeds 2 kV (HBM)

• Available in 5-mm × 5-mm QFN-28 (RHD)

Package

2 Applications

• Wireless Communications

• Telecommunications/Networking

• Medical Imaging

• Test and Measurement Equipment

3 Description

The CDCLVP1208 is a highly versatile, low additive

jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL,

LVDS, or LVCMOS inputs for a variety of

communication applications. It has a maximum clock

frequency up to 2 GHz. The CDCLVP1208 features

an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a

control terminal. The overall additive jitter

performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 20 ps,

making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of

differential LVPECL clock outputs (OUT0, OUT7) with

minimum skew for clock distribution. The

CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS,

or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) should be applied to the unused negative

input terminal. However, for high-speed performance

up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin,

5-mm x 5-mm QFN package and is characterized for

operation from –40°C to 85°C.