Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

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Dual 1:6 Low Additive Jitter LVDS Buffer

文件：919.72 Kbytes 页数：22 Pages

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德州仪器

Dual 1:6 Low Additive Jitter LVDS Buffer

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德州仪器

丝印：CDCLVD2106；Package：VQFN；Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

文件：809.46 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CDCLVD2106；Package：VQFN；Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

文件：809.46 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CDCLVD2106；Package：VQFN；Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

文件：809.46 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CDCLVD2106；Package：VQFN；Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

文件：809.46 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CDCLVD2106；Package：VQFN；Dual 1:6 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:6 Differential Buffer • Low Additive Jitter:

文件：809.46 Kbytes 页数：20 Pages

TI

德州仪器

低抖动双路 1:6 通用至 LVDS 缓冲器

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2106 is specifically designed for drivi • Dual 1:6 Differential Buffer\n• Low Within Bank Output Skew of 45 ps (Max)\n• One Input Dedicated for Six Outputs\n• Clock Frequency up to 800 MHz\n• LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs\n• Packaged in 6 mm × 6 mm 40-pin QFN (RHA)\n• APPLICATIONS \n• Medical Ima;

TI

德州仪器

Dual 1:6 Low Additive Jitter LVDS Buffer

文件：919.72 Kbytes 页数：22 Pages

TI

德州仪器