CDCLVD110A中文资料通过超小偏斜实现时钟分配且频率高达 1100MHz 的 1:10 LVDS 时钟缓冲器数据手册TI规格书

描述 Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.The CDCLVD110A is characterized for operation from –40°C to 85°C.

特性 Features

• Low-Output Skew CC Range: 2.5 V ±5%
• Typical Signaling Rate Capability of Up to 1.1 GHz
• Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
• Full Rail-to-Rail Common-Mode Input Range
• Receiver Input Threshold: ±100 mV
• Available in 32-Pin LQFP and VQFN Package
• Fail-Safe I/O-Pins for VDD = 0 V (Power Down)