3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 页数：14 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：132.48 Kbytes 页数：9 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes 页数：13 Pages

TI

德州仪器

3.3V 相位锁定环路时钟驱动器

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3 • Use CDCVF2509A as a Replacement for this Device\n• Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n• Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs\n• Separate Output Enable for Each Output Bank\n• External Feedback (FBIN) Pin Is Used to Synchron;

TI

德州仪器

丝印：CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 页数：14 Pages

TI

德州仪器

丝印：CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 页数：14 Pages

TI

德州仪器

丝印：CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 页数：14 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes 页数：13 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：132.48 Kbytes 页数：9 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes 页数：13 Pages

TI

德州仪器