丝印：CDC2516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：1.06695 Mbytes 页数：17 Pages

TI

德州仪器

Pulse-Load Battery Monitor

Description The CS2516 is designed for use in battery powered medical, security, or environmental systems where prior notification of impending power source failure is a requirement. The IC effectively provides continuous monitoring of battery condition by pulsesampling the system voltage at pred

文件：143.67 Kbytes 页数：6 Pages

CHERRY

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate (DDR) architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 页数：2 Pages

KINGSTON

金士顿

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver • DOS

文件：425.79 Kbytes 页数：2 Pages

KINGSTON

金士顿