CD74HC4017PW集成电路（IC）的计数器除法器规格书PDF中文资料

厂商型号	CD74HC4017PW
参数属性	CD74HC4017PW 封装/外壳为16-TSSOP（0.173"，4.40mm 宽）；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的计数器除法器；产品描述：IC DECADE COUNTR/DIVIDER 16TSSOP
功能描述	High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
封装外壳	16-TSSOP（0.173"，4.40mm 宽）
文件大小	738.58 Kbytes
页面数量	22 页
生产厂商	TI
中文名称	德州仪器
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-10-12 11:18:00
人工找货	CD74HC4017PW价格和库存，欢迎联系客服免费人工找货

特性 Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Positive Edge Clocking

• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

描述 Description

The ’HC4017 is a high speed silicon gate CMOS 5-stage

Johnson counter with 10 decoded outputs. Each of the

decoded outputs is normally low and sequentially goes high

on the low to high transition clock period of the 10 clock

period cycle. The CARRY (TC) output transitions low to high

after OUTPUT 10 goes from high to low, and can be used in

conjunction with the CLOCK ENABLE (CE) to cascade

several stages. The CLOCK ENABLE input disables

counting when in the high state. A RESET (MR) input is also

provided which when taken high sets all the decoded

outputs, except “0”, low.

The device can drive up to 10 low power Schottky equivalent

loads.