丝印：CD74HC109E；Package：PDIP；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

文件：367.45 Kbytes 页数：16 Pages

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德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件：347.95 Kbytes 页数：16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件：454.62 Kbytes 页数：15 Pages

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德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件：279.59 Kbytes 页数：12 Pages

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德州仪器