丝印：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.26 Kbytes 页数：11 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：56.86 Kbytes 页数：8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：451.69 Kbytes 页数：15 Pages

TI

德州仪器