CD74ACT109E.A规格书应用电路贸易商TI-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
CD74ACT109E.A	文件：412.14 Kbytes Page：14 Pages	丝印：CD74ACT109E；Package：PDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, 文件：412.14 Kbytes 页数：14 Pages	TI 德州仪器	TI
CD74ACT109M	文件：337.77 Kbytes Page：10 Pages	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 文件：337.77 Kbytes 页数：10 Pages	TI 德州仪器	TI
CD74ACT109M	文件：349.71 Kbytes Page：11 Pages	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 文件：349.71 Kbytes 页数：11 Pages	TI 德州仪器	TI
CD74ACT109M	文件：412.14 Kbytes Page：14 Pages	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, 文件：412.14 Kbytes 页数：14 Pages	TI 德州仪器	TI

更多CD74ACT109E.A供应商更新时间2025-12-13 15:01:00