丝印：CD74AC109E；Package：PDIP；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

文件：1.09024 Mbytes 页数：22 Pages

TI

德州仪器

Dual JK Positive Edge-triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop

文件：346.23 Kbytes 页数：5 Pages

AVG

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inp

文件：170.71 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inp

文件：224.51 Kbytes 页数：6 Pages

IKSEMICON