CD54HCT4024数据手册TI中文资料规格书

描述 Description

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

特性 Features

• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
• Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
• Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
• 2V to 6V Operation
• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

• HCT Types
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH