CD54HCT165中文资料高速 CMOS 逻辑 8 位并行输入/串行输出移位寄存器数据手册TI规格书

描述 Description

The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q7 and Q\\7) available from the last stage. When the parallel load (PL\\) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL\\ is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allow parallel-to-serial converter expansion by typing the Q7 output to the DS input of the succeeding device.

For predictable operation the LOW-to-HIGH transition of CE\\ should only take place while CP is HIGH. Also, CP and CE\\ should be LOW before the LOW-to-HIGH transition of PL to prevent shifting the data when PL\\ goes HIGH.

特性 Features

• Buffered Inputs
• Complementary Outputs
• Standard Outputs. . . . . . 10 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Significant Power Reduction Compared to LSTTL Logic ICs
• 2V to 6V Operation
• HCT Types
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH