CD54HC75中文资料高速 CMOS 逻辑双路 2 位双稳态透明锁存器数据手册TI规格书

描述 Description

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\\ and 2E\\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\\ and 2E\\) is LOW the output is not affected.

特性 Features

• True and Complementary Outputs
• Fanout (Over Temperature Range)
• Bus Driver Outputs...15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• HC Types
• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH
Data sheet acquired from Harris Semiconductor