丝印：CD54HC73F；Package：CDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 页数：24 Pages

TI

德州仪器

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology ■ HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

文件：247.47 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：317.55 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

Rad-hard high speed 2 to 6 V CMOS logic series

文件：306.74 Kbytes 页数：29 Pages

STMICROELECTRONICS

意法半导体