CD54HC194中文资料高速 CMOS 逻辑 4 位双向通用移位寄存器数据手册TI规格书

描述 Description

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\\ pin.

特性 Features

• Four Operating Modes
• Synchronous Parallel or Serial Operation
• Asynchronous Master Reset
• Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• HC Types
• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH