丝印：8408801EA；Package：CDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 页数：29 Pages

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德州仪器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes 页数：13 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes 页数：18 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes 页数：20 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes 页数：20 Pages

TI

德州仪器