Dual 4-Bit, 8-Bit Addressable Latch

文件：146.84 Kbytes 页数：8 Pages

NSC

国半

CMOS 8-BIT ADDRESSABLE LATCH

文件：1.0139 Mbytes 页数：13 Pages

TI

德州仪器

Dual 4-Bit, 8-Bit Addressable Latch

文件：146.84 Kbytes 页数：8 Pages

NSC

国半

Dual 4-Bit, 8-Bit Addressable Latch

文件：146.84 Kbytes 页数：8 Pages

NSC

国半

CMOS 8-Bit Addressable Latch

文件：437.45 Kbytes 页数：10 Pages

TI

德州仪器

CMOS 8-Bit Addressable Latch

文件：437.45 Kbytes 页数：10 Pages

TI

德州仪器

CMOS 8 位可寻址锁存器

CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.\n Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is • Serial data input\n• Storage register capability\n• Can function as demultiplexer\n• 100% tested for quiescent current at 20 V\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tent;

TI

德州仪器

CMOS 8 位可寻址锁存器

CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.\n Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is • Serial data input\n• Storage register capability\n• Can function as demultiplexer\n• 100% tested for quiescent current at 20 V\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tent;

TI

德州仪器

CMOS 8-Bit Addressable Latch

Renesas

瑞萨

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 锁存器 描述：IC ADDRESSABLE LATCH 8BIT 16SOIC

ONSEMI

安森美半导体