丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

CMOS 4-Bit Latch/4-to-16 Line Decoders

Description CD4514BMS and CD4515BMS consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514BMS) or 1(CD4515BMS) regardless of the state of

文件：92.13 Kbytes 页数：9 Pages

Intersil

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes 页数：12 Pages

TI

德州仪器

4-Bit Latched/4-to-16 Line Decoders

文件：135.98 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes 页数：15 Pages

TI

德州仪器