丝印：CD4508B；Package：SOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508B；Package：SOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508B；Package：SOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器