CD4508B-MIL中文资料CMOS 双路 4 位锁存器数据手册TI规格书

描述 Description

CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the \"D\" inputs appear at the corresponding \"Q\" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.

The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).

The CD4508B is similar to industry type MC14508.

特性 Features

• Two independent 4-bit latches
• 3-state outputs with high-impedance state for bus line applications
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V
• Applications:
• Holding registers
• Data storage and multiplexing