CD4502B中文资料6 通道、3V 至 18V 反相器数据手册TI规格书

描述 Description

CD4502B consists of six inverter/buffers with 3-state outputs. A logic \"1\" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic \"1\" on the INHIBIT input switches all six outputs to logic \"0\" if the OUTPUT DISABLE input is a logic \"0\". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC \"B\"-series IOL standard.

The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• 2 TTL-load output drive capability
• Common output-disable control
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise Margin (full package-temperature range) =    1 V at VDD = 5 V    2 V at VDD = 10 V    2.5 V at VDD = 15 V
• 3-state hex inverter for interfacing IC's with data buses
• COS/MOS to TTL hex buffer

简介

CD4502B属于集成电路（IC）的缓冲器驱动器接收器收发器。由TI制造生产的CD4502B缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。