CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 页数：12 Pages

TI

德州仪器

CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 页数：12 Pages

TI

德州仪器

CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 页数：12 Pages

TI

德州仪器

CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 页数：12 Pages

TI

德州仪器

CMOS 可扩展 4 宽度 2 输入与或非门

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is requir • Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V\n• INHIBIT and ENABLE inputs\n• Buffered outputs\n• 100% tested for quiescent current at 20 V\n• Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (over full pac;

TI

德州仪器

CMOS 可扩展 4 宽度 2 输入与或非门

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is requir • Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V\n• INHIBIT and ENABLE inputs\n• Buffered outputs\n• 100% tested for quiescent current at 20 V\n• Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (over full pac;

TI

德州仪器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

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Package：14-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 - 多功能，可配置 描述：IC EXPND AND-ORINV GATE 14-SOIC

TI

德州仪器

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 - 多功能，可配置 描述：IC EXPND AND-ORINV GATE 14-SOIC

TI

德州仪器

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 - 多功能，可配置 描述：IC EXPND AND-ORINV GATE 14-SOIC

TI

德州仪器