CMOS OR Gate

Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Featu

文件：114.68 Kbytes 页数：10 Pages

Intersil

CMOS OR GATES

文件：209.38 Kbytes 页数：5 Pages

TI

德州仪器

CMOS OR Gate

Description\nCD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.\nThe CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: • High-Voltage Types (20V Rating)\n• CD4071BMS Quad 2-Input OR Gate\n• CD4072BMS Dual 4-Input OR Gate\n• CD4075BMS Triple 3-Input OR Gate\n• Medium Speed Operation:\n- tPHL, tPLH = 60ns (typ) at 10V\n• 100% Tested for Quiescent Current at 20V\n• Maximum Input Current of 1µA at 18V Over Full Pack;

Renesas

瑞萨

双四路或门

正双四路输入,工作电压（Vcc）(v)3~15V,静态电流Iq(Typ)0.01uA

XBLW

芯伯乐

Dual 4-input OR gate

I-CORE

中微爱芯

CMOS OR Gate

Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Featu

文件：114.68 Kbytes 页数：10 Pages

Intersil

CMOS OR Gate

Features • High-Voltage Types (20V Rating) • CD4071BMS Quad 2-Input OR Gate • CD4072BMS Dual 4-Input OR Gate • CD4075BMS Triple 3-Input OR Gate • Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V • 100 Tested for Quiescent Current at 20V • Maximum Input Current of 1A at 18V Over Fu

文件：396.79 Kbytes 页数：11 Pages

RENESAS

瑞萨

CMOS OR Gates

文件：1.63591 Mbytes 页数：29 Pages

TI

德州仪器

CMOS OR GATES

文件：209.38 Kbytes 页数：5 Pages

TI

德州仪器

CMOS OR GATES

文件：524.26 Kbytes 页数：12 Pages

TI

德州仪器