CD4046B数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary.
The CD4046B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Very low power consumption:    70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
- Exclusive-OR network (I)
• Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: DD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod. output)
• Zener diode to assist supply regulation
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"
• Applications
- FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discriminator
• Data synchronization
• Voltage-to-frequency conversion
• Tone decoding
• FSK - Modems
• Signal conditioning
• (See ICAN-6101) \"RCA COS/MOS Phase-Locked Loop - A Versatile Building Block for Micropower Digital and Analog Applications\"