CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes 页数：16 Pages

TI

德州仪器

CMOS 4 级并行输入/并行输出移位寄存器

CD4035B is a four-stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK\\ logic.Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERI • 4-Stage clocked shift operation\n• JK\\ inputs on first stage\n• Static flip-flop operation; Master-slave configuration\n• High speed — 12 MHz (typ.) at VDD = 10 V\n• Standardized, symmetrical output characteristics\n• Meets all requirements of JEDEC Tentative Standard No. 13A, \"Standard Specific;

TI

德州仪器

CMOS 4 -Stage Parallel In/Parallel Out Shift Register

文件：118.61 Kbytes 页数：10 Pages

INTERSIL

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes 页数：17 Pages

TI

德州仪器

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes 页数：16 Pages

TI

德州仪器