CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器

CMOS PRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET)

文件：516.35 Kbytes 页数：11 Pages

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德州仪器

CMOs Presettable Up/Down counters

文件：1.11003 Mbytes 页数：15 Pages

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德州仪器

丝印：CD40193B；Package：SOP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD40193B；Package：SOP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD40193B；Package：SOP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

文件：74.66 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

文件：74.66 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

丝印：CD40193BE；Package：PDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD40193BE；Package：PDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 页数：20 Pages

TI

德州仪器