CD4018B

CMOS 可预置 N 分频计数器; • Medium speed operation……10 MHz (typ.) at VDD – VSS = 10 V\n• Fully static operation\n• 100% tested for quiescent current at 20 V\n• Standardized, symmetrical output characteristics\n• 5-V, 10-V, and 15-V parametric ratings\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n• Applications: \n• Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters\n• Fixed and programmable counters greater than 10\n• Programmable decade counters\n• Divide-by-\"N\" counters/frequency synthesizers\n• Frequency division\n• Counter control/timers;

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\\5, Q\\4, Q\\3, Q\\2, Q\\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.\n\n The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4018B

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

CD4018B-MIL

CMOS 可预置 N 分频计数器; • Medium speed operation……10 MHz (typ.) at VDD – VSS = 10 V\n• Fully static operation\n• 100% tested for quiescent current at 20 V\n• Standardized, symmetrical output characteristics\n• 5-V, 10-V, and 15-V parametric ratings\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n• Applications: \n• Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters\n• Fixed and programmable counters greater than 10\n• Programmable decade counters\n• Divide-by-\"N\" counters/frequency synthesizers\n• Frequency division\n• Counter control/timers;

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\\5, Q\\4, Q\\3, Q\\2, Q\\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.\n\n The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4018BMS

CMOS Presettable Divide-By- “N” Counter

Description CD4018BMStypesconsistof5Johnson-Counterstages,bufferedQoutputsfromeachstage,andcounterpresetcontrolgating. Features •HighVoltageType(20VRating) •MediumSpeedOperation10MHz(typ.)atVDD-VSS=10V •FullyStaticOperation •100TestedforQ

CD4018B_15

CMOS Presettable Divide-by -N counter

CD4018BE

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

CD4018BE

CMOS Presettable Divide-by -N counter

CD4018BEE4

CMOS Presettable Divide-by -N counter

CD4018BF

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

CD4018BF

CMOS Presettable Divide-by -N counter