CD4017中文资料5阶Johnson译码计数器数据手册I-CORE规格书

描述 Description

The CD4017 is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q(—)5-9), active HIGH and active LOW clock inputs (CP0, CP(—)1) and an overriding asynchronous master reset input (MR).The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP(—)1 is LOW or a HIGH-to-LOW transition at CP(—)1 while CP0 is HIGH.When cascading counters, the Q(—)5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0=Q(—)5-9=HIGH; Q1 to Q9=LOW) independent of the clock inputs (CP0, CP(—)1).Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

特性 Features

• Wide supply voltage range from 3V to 15V
• Automatic counter correction
• Tolerant of slow clock rise and fall times
• 5V, 10V, and 15V parametric ratings
• Standardized symmetrical output characteristics
• Specified from -40℃ to +125℃
• Packaging information: DIP16/SOP16/TSSOP16

应用 Application

• 家用电器
• 工业控制
• 新能源