CD4015B中文资料CMOS 双路 4 级静态移位寄存器数据手册TI规格书

描述 Description

CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. \"Q\"outputs are available from each of the four stages on both registers. All register stages are D-type,master-slave flip-flops. The logic level present at the DATA input is transferred into the firstregister stage and shifted over one stage at each positive-going clock transition. Resetting of allstages is accomplished by a high level on the reset line. Register expansion to 8 stages using oneCD4015B package, or to more than 8 stages using additional CD4015B’s is possible.
The CD4015B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Medium speed operation...12 MHz (typ.) clock rate at VDD – VSS = 10 V
• 8 master-slave flip-flops plus input and output buffering
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 2 V at VDD = 10 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of’B’ Series CMOS Devices\"
• Serial to parallel data conversion
• General-purpose register
Data sheet acquired from Harris Semiconductor