CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

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德州仪器

CMOS NAND GATES

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德州仪器

CMOS NAND GATES

文件：1.29026 Mbytes 页数：20 Pages

TI

德州仪器

军用 4 通道、2 输入、3V 至 18V 与非门

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NANDfunction and supplement the existing family of CMOS gates. All inputs and outputs are buffered.\n\n The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic • Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n• Standardized symmetrical output characteristics\n• 100% tested for quiescent current at 20 V\n• Noise margin (over full package temperature range:     1 V at VDD = 5 V     2 V at VDD = 10 V     2.5 at VDD = 15 V\n• Meets all re;

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德州仪器