CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：CD40102B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40102B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40102BE；Package：PDIP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40102BE；Package：PDIP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

文件：166.83 Kbytes 页数：13 Pages

INTERSIL

丝印：CM0102B；Package：TSSOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CM0102B；Package：TSSOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CM0102B；Package：TSSOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器