CD40102B

CMOS 8 级可预置 2 位十进制 BCD 同步递减计数器; • Synchronous or asynchronous preset\n• Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V\n• Cascadable\n• 100% tested for quiescent current at 20 V\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Standardized, symmetrical output characteristics\n• 5-V, 10-V, and 15-V parametric ratings\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n• Applications: \n• Divide-by-\"N\" counters\n• Programmable timers\n• Interrupt timers\n• Cycle/program counter\n \n CD40102B - 2-Decade BCD Type CD40103B - 8-Bit Binary Type;

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.\n\n In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\\ output goes low when the count reaches zero if the CI/CE\\ input is low, and remains low for one full clock period.\n\n When the SYNCHRONOUS PRESET-ENABLE (SPE)\\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\\, CI/CE\\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\\ input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102B and 25510 for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.\n\n If all control inputs except CI/CE\\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.\n\n This causes the CO/ZD\\ output to go low to enable the clock on each succeeding clock pulse.\n\n The CD40102B and CD40103B may be cascaded using the CI/CE\\ input and CO/ZD\\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22.\n\n The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

CD40102BMS

CMOS 8-Stage Presettable Synchronous Down Counters; • High Voltage Type (20V Rating)\n• CD40102BMS: 2-Decade BCD Type\n• CD40103BMS: 8-Bit Binary Type\n• Synchronous or Asynchronous Preset\n• Medium Speed Operation\n   - fCL = 3.6MHz (Typ) at 10V\n• Cascadable\n• 100% Tested for Quiescent Current at 20V\n• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC\n• Noise Margin (Over Full Package/Temperature Range)\n   - 1V at VDD = 5V\n   - 2V at VDD = 10V\n   - 2.5V at VDD = 15V\n• Standardized Symmetrical Output Characteristics\n• 5V, 10V and 15V Parametric Ratings\n• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”Applications\n• Divide-By- “N” Counters\n• Programmable Times\n• Interrupt Timers\n• Cycle/Program Counter ;

Description\nCD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.

CD40102BMS

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMSandCD40103BMSconsistofan8-stagesynchronousdowncounterwithasingleoutputwhichisactivewhentheinternalcountiszero.TheCD40102BMSisconfiguredastwocascaded4-bitBCDcounters,andtheCD40103BMScontainsasingle8-bitbinarycounter.Eachtypehasc

CD40102B

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

CD40102B_15

CMOS 8-stage Presettable Synchronous Down Counters

CD40102BE

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

CD40102BE

CMOS 8-stage Presettable Synchronous Down Counters

CD40102BEE4

CMOS 8-stage Presettable Synchronous Down Counters

CD40102BNSR

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

CD40102BNSR

CMOS 8-stage Presettable Synchronous Down Counters