CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

文件：29.89 Kbytes 页数：3 Pages

INTERSIL

丝印：CD4011BE；Package：PDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BE；Package：PDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BE；Package：PDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BF；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BF；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BF3A；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4011BF3A；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

文件：176.66 Kbytes 页数：5 Pages

UTC

友顺

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

文件：29.89 Kbytes 页数：3 Pages

INTERSIL