CD4002B中文资料2 通道、4 输入、3V 至 18V 或非门数据手册TI规格书

描述 Description

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR functionand supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and14-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Standardized symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range):      1 V at VDD = 5 V      2 V at VDD = 10 V   2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"
Data sheet acquired from Harris Semiconductor