CMOS NOR Gates

文件：952.17 Kbytes 页数：19 Pages

TI

德州仪器

CMOS NOR Gates

文件：952.17 Kbytes 页数：19 Pages

TI

德州仪器

CMOS NOR Gates

文件：1.18416 Mbytes 页数：18 Pages

TI

德州仪器

CMOS NOR Gates

文件：523.679 Kbytes 页数：12 Pages

TI

德州仪器

CMOS NOR Gates

文件：952.17 Kbytes 页数：19 Pages

TI

德州仪器

CMOS NOR Gates

文件：952.17 Kbytes 页数：19 Pages

TI

德州仪器

CMOS NOR Gates

文件：952.17 Kbytes 页数：19 Pages

TI

德州仪器

CMOS NOR Gates

文件：1.18416 Mbytes 页数：18 Pages

TI

德州仪器

2 通道、4 输入、3V 至 18V 或非门

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR functionand supplement the existing family of CMOS gates. All inputs and outputs are buffered.\n\n The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic p • Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n• Standardized symmetrical output characteristics\n• 5-V, 10-V, and 15-V parametric ratings\n• Noise margin (over full package temperature range):      1 V at VDD = 5 V      2 V at VDD = 10 V   2.5 V at VDD = 15 V\n• Meets all requi;

TI

德州仪器

军用 2 通道、4 输入、3V 至 18V 或非门

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR functionand supplement the existing family of CMOS gates. All inputs and outputs are buffered.\n\n The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic p • Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n• Standardized symmetrical output characteristics\n• 5-V, 10-V, and 15-V parametric ratings\n• Noise margin (over full package temperature range):      1 V at VDD = 5 V      2 V at VDD = 10 V   2.5 V at VDD = 15 V\n• Meets all requi;

TI

德州仪器