PowerMOS transistor Logic level TOPFET

DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. FEATURES ● TrenchMOS output stage ● Current limiting ● Overload protection ● Overtemperature protection ● Protection latched reset by

文件：72.69 Kbytes 页数：11 Pages

恩XP

PowerMOS transistor Logic level TOPFET

DESCRIPTION\nMonolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package.FEATURES\n● TrenchMOS output stage\n● Current limiting\n● Overload protection\n● Overtemperature protection\n● Protection latched reset by inpu ● TrenchMOS output stage\n● Current limiting\n● Overload protection\n● Overtemperature protection\n● Protection latched reset by input\n● 5 V logic compatible input level\n● Control of output stage and supply of overload protection\n   circuits derived from input\n● Low operating input current permi;

恩XP

PowerMOS transistor Logic level TOPFET

DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. FEATURES ● TrenchMOS output stage ● Current trip protection ● Overload protection ● Overtemperature protection ● Protection latched re

文件：53.36 Kbytes 页数：7 Pages

PHI

PHI

D2PAK

NEXPERIA

安世

上传：万三科技(深圳)有限公司

D2PAK

NEXPERIA/安世

上传：深圳市盈慧通电子有限公司